4 X 10G and 100G BERT (above)
Description:
4 X 25Gbps (100G) BERT (Bit Error Rate Tester) is designed to test cables and diagnose signal problems in the communication field. 4-channel Standard Multi-rate between 25.78Gbps and 27.95Gbps are provided for signal conditioning and BER analysis. OEM model is well available on customer’s special request.
Applications:
Communications IC test
PON Systems
Telecommunication systems
Data communication systems
CFP2/CFP4/QSFP28/SFP28
Features:
4-channel standard multi-rate BERT between 25.78Gbps and 27.95Gbps
PRBS7/9/15/23/31 pattern or clock generation and error detection with integrated clock data recovery
High speed trigger output
Automatically synchronized alignment
Output connector can be compatible with PRC-3.5 and SMA
Easy-to-use and cost-effective
Specifications:
Parameters |
Symbol |
MIN |
TYP |
Max |
UNIT |
NOTE |
Data Rate |
DR |
25.78 |
|
27.9 |
Gbps |
|
No. of channels |
|
|
4 |
|
|
|
PRBS Pattern 2N-1 |
N |
7/9/15/23/31 |
|
|
Data input Termination |
AC-Coupled |
|
Data Output Amplitude |
T_Vdiff |
600 |
|
|
mV |
|
Data Output Termination |
AC-Coupled |
|
Data Output Resistance |
T_Rd |
85 |
100 |
115 |
ohm |
Differential |
Data input Resistance |
R_Rdin |
85 |
100 |
115 |
ohm |
|
Data input Termination |
AC-Coupled |
|
Trigger output Frequency |
ftriout |
3.2225 |
|
3.4875 |
Gbps |
Data rate/8 |
Trigger output Termination |
AC-Coupled |
|
clk output Frequency |
fclkout |
644.5312 |
|
698.8123 |
Mbps |
Data rate/40 |
clk output Termination |
AC-Coupled |
|
ext clk Input Duty Cycle |
CK_DCD |
40 |
|
60 |
% |
|
ext clk Input Amplitude |
CK_Vin |
600 |
|
1600 |
mVdpp |
|
Warm Up Time |
Twu |
10 |
|
|
S |
|
Operating Temperature |
Top |
10 |
|
40 |
oC |
Ambient Temp |
Power Consumption |
APwr |
|
|
5 |
W |
25 ℃ ambient temp |
Operating System
Figure 1. Typical eye diagram of pattern generator electrical output (above)
Ordering Information
Part Number |
Description |
BERT100 |
4 X 25Gbps BERT |